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Physical Design Level -3

What are disadvantages of CCD?

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CTS

What are preplaced cells?

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PNR

What will happen if insertion delay of clock is high?

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PNR

Suppose,if you have 20k feedthroughs going from your block 10 k are going from left to right and 10k from top to bottom what is special care you will taking while placing macros ?

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PNR

In VLSI Physical Design, why don't we route before CTS?

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PNR

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